Unlike standard computer memory (random access memory or RAM) in which the user supplies a memory address and the RAM returns the data word stored at that address, a content addressable memory (CAM) is designed such that the user supplies a data word and the CAM searches its entire memory to see if that data word is stored anywhere in it. If the data word is found, the CAM returns a list of one or more storage addresses where the word was found.
Because a CAM is designed to search its entire memory in a single operation, it is much faster than RAM in virtually all search applications. However, there are cost disadvantages to CAM. Unlike a RAM chip, which has simple storage cells, each individual memory bit in a fully parallel CAM must have its own associated comparison circuit to detect a match between the stored bit and the input bit. Additionally, match outputs from each cell in the data word must be combined to yield a complete data word match signal. The additional circuitry increases the physical size of the CAM chip which increases manufacturing cost. The extra circuitry also increases power dissipation since every comparison circuit is active on every clock cycle. Consequently, CAMs are only used in specialized applications where searching speed cannot be accomplished using a less costly method.
Despite the cost disadvantages associated with CAMs, attempts have been made to integrate CAM functionality within general purpose programmable logic devices. However, previous such attempts have not been commercially successful. One reason this is so is because usage of CAMs varies widely in the width of the comparison field. Different CAM applications can require widths from 16 bits up to 360 bits. Memories and hence hard CAMs offered by these FPGAs have very limited variation in width, usually only up to 36 bits wide. This limitation is at odds with a FPGA's goal of handling a wide variety of applications, such as supporting exact and associative look-ups with a very wide variety of widths.
A real-time reconfigurable device reconfigures to execute each portion of a design in an automatically defined sequence of steps. Such a programmable device can reconfigure on the fly at multi-GHz rates to support higher density memories and routing resources. There is therefore a need for integrating CAM functionalities into a real-time reconfigurable device such that the speed advantages of CAM functionality can be realized at minimal additional cost. There is also a need for such a real-time reconfigurable device to support a wide range of applications, including exact and associative look-ups at a very wide variety of widths.